A circuit system usually has a clock input and data inputs. The clock input can drive various components in the circuit system at a rising edge of the clock signal. The components responding to the rising edge need their inputs “held” constant for a small time past the rising edge, reducing the portion of the clock period available for useful computation and thus reducing circuit performance. Latches can be used for sequential components as a cost-efficient solution in a circuit system. At a low overhead cost, a latch can serve in a similar way to a flip-flop by pulsing the enable pin of the latch. However, such pulsed latches may induce a longer hold-time that is difficult for a short data path with little or no logic to mitigate.